1. Field of the Invention
This invention relates to a clock signal regeneration method and apparatus for regenerating a clock signal synchronized with received data, and more particularly to a clock signal regeneration method and apparatus for use in the field of digital radio communications wherein, from received data, a timing signal corresponding to the rate of the received data is extracted and compared in phase with a regenerated clock signal outputted from the clock signal regeneration apparatus to produce a phase difference signal corresponding to the difference in phase between the timing signal and the regenerated clock signal and then the phase of the regenerated clock signal is corrected based on the phase difference signal.
2. Description of the Related Art
Such a clock signal regeneration apparatus as shown in FIG. 8 is conventionally known as a clock signal regeneration apparatus which employs a phase locked loop (PLL). Referring to FIG. 8, the clock signal regeneration apparatus shown includes a timing extraction circuit 101 for extracting, from received data, a timing signal corresponding to the rate of the received data, a phase comparator 102 for comparing the phases of the timing signal extracted by the timing extraction circuit 101 and a regenerated clock signal outputted from the clock signal regeneration apparatus with each other and outputting a phase difference signal of a voltage corresponding to the phase difference, a loop filter (low-pass filter) 103 for removing high frequency components from the phase difference signal from the phase comparator 102, an addition/subtraction control circuit 104, a count value correction circuit 105, and a counter 106 for counting pulses of a controlling clock signal (FAST CLOCK) having a frequency N times that of the timing signal.
The addition/subtraction control circuit 104 outputs, in response to a phase difference voltage outputted from the loop filter 103, a signal indicating whether the count value of the counter 106 should be incremented or decremented by one. The count value correction circuit 105 corrects the current count value of the counter 106 in response to the output of the addition/subtraction control circuit 104 and loads the thus corrected count value into the counter 106 in response to the regenerated clock signal of the clock signal regeneration apparatus.
By the operation Just described, the counter 106 modifies its count value in accordance with a phase difference between the timing signal extracted from the received data and the regenerated clock signal, and controls the phase of the regenerated clock signal with a step equal to 1/N of the step at the data rate of the received data. This operation plays the role of a voltage controlled oscillator (VCO) of a PLL circuit so that a clock signal corresponding to the rate of the received data is regenerated.
The phase control of the regenerated clock signal of the conventional apparatus described above, however, has an upper limit defined by the width of one clock of the controlling clock signal and only allows phase control in minimum units of the thus limited fixed width. In particular, where the controlling clock signal has a rate equal to N times the data rate, the phase of the regenerated clock signal cannot be corrected with a step smaller than 1/N of the step at the data rate. This relationship is illustrated in a time chart of FIG. 9. Referring to FIG. 9, where the data are such as illustrated by the curve (1), the curve (2) illustrates a regenerated clock signal which is displaced in phase from the data signal by an amount equal to a minimum phase control width .alpha. of one step while the curve (3) illustrates another regenerated clock signal which is corrected optimally in phase. In this instance, the minimum phase control width .alpha. is equal to 1/N of the width of one symbol of the data, or in other words, equal to the width of one clock of the controlling clock signal.
Accordingly, in a system in which a large amount of data is processed at a high speed, when the rate of data is so high that the ratio "N" between the symbol rate of the data (the symbol rate signifies the number of symbols which can be transmitted within one second; the symbol rate is equal to the bit rate where the data are binary digital modulation data, but is equal to 1/2 the bit rate where the data are four-value digital modulation data) and the rate of the controlling clock signal cannot be set high, the regenerated clock signal exhibits high phase jitters, and consequently, a high performance of the system cannot be assured. Further, if it is intended to suppress the phase jitters of the regenerated clock signal, then the frequency of the controlling clock signal must be set extremely high. For example, if it is tried to suppress phase jitters within 3.degree. with the data rate of 2.5 Mb/s, then the frequency of the controlling clock signal must be 300 MHz or more. This value is not actually practical.